Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - stopwatch vhdl

Search list

[Other] jishu

Description: 基于VHDL的计时秒表 59分59秒59 具有计时暂停功能 通过数码管显示-Timing stopwatch 59.59.59 with timing suspended through digital tube display please enter the text to be translated
Platform: | Size: 139264 | Author: 温中意 | Hits:

[VHDL-FPGA-Verilog] JiShuQi

Description: 实现了一个秒表计数器，输入为2MHZ时钟，使用VHDL语言实现-It implements a stopwatch counter input 2MHZ clock, using VHDL language
Platform: | Size: 303104 | Author: 黄予 | Hits:

[Documents] VHDLtime

Description: 实现秒表设计，实现秒、百分秒之间的相互切换，初级VHDL代码-Realize stopwatch design, implementation seconds, percentage of seconds to switch between each other, the primary VHDL code
Platform: | Size: 19535872 | Author: 张宏达 | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 使用VHDL\FPGA实现秒表的设计，包含所有源码。-Use VHDL\FPGA to achieve a stopwatch
Platform: | Size: 1520640 | Author: 梁坤 | Hits:

[VHDL-FPGA-Verilog] practise

Description: FPGA实验板设计一个数字跑表。根据题目要求利用VHDL语言设计出一个系统，包括分频器，开关消抖，使能控制，计数器，锁存器，数据选择器及显示译码器。-FPGA experimental board design a digital stopwatch. According to subject the use of VHDL language to design a system, including the divider, switch debounce, enable control, counters, latches, and display the data selector decoder.
Platform: | Size: 6653952 | Author: 郑晓 | Hits:

[VHDL-FPGA-Verilog] ELECTRONICCLOCK

Description: VHDL语言设计的电子钟，并且有暂停功能和清零功能的按键实现，并且带秒表-VHDL language design electronic clock, and there is a pause function and achieve clear function buttons, and with stopwatch
Platform: | Size: 6144 | Author: 安迪 | Hits:

[VHDL-FPGA-Verilog] VHDL_paobiao

Description: 用VHDL语言设计一个跑表，计时范围为59.99秒。-Write a time range using VHDL language to 59.99 seconds in the stopwatch
Platform: | Size: 113664 | Author: wangcong | Hits:

[VHDL-FPGA-Verilog] swfsm

Description: stopwatch的FSM状态机的代码，可供初学者学习参考如何编写状态机-the finite state machine vhdl code for the simple stopwatch file
Platform: | Size: 2048 | Author: Echo Li | Hits:

[VHDL-FPGA-Verilog] VHDLstopwatch

Description: 采用vhdl硬件描述语言实现的秒表计时器程序源码及顶层电路设计图，实现了计时器，数码管显示，按键控制及蜂鸣器等功能-Using VHDL hardware description language to realize the stopwatch timer program source code and top-level circuit design, the timer, digital tube display, control buttons and a buzzer function
Platform: | Size: 217088 | Author: 林之钊 | Hits:

[Software Engineering] chronometer

Description: You can use this to build a stopwatch on a nexys 3 board in VHDL.
Platform: | Size: 2310144 | Author: Mouhcine | Hits:

[VHDL-FPGA-Verilog] dig_watch

Description: fpga实验，基于VHDL语言的数字跑表设计，其中包含有存储模块。-Fpga experiment, the digital stopwatch designed based on VHDL language, which contains a storage module.
Platform: | Size: 3205120 | Author: 张鹏飞 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: 韩福柱老师FPGA实验源码，用vhdl语言在xilinx FPGA上实现，包括ad采集，温度传感器读取，秒表，跑马灯和按键次数统计4个实验-Han Fu teacher FPGA column experiment source code, vhdl languages on xilinx FPGA implementations, including ad acquisition, temperature sensor readings, stopwatch, marquees and keystrokes 4 experimental statistics
Platform: | Size: 8192 | Author: Jery | Hits:

[Embeded-SCM Develop] clock

Description: 本个程序主要通过vhdl来实现一个秒表的设计-This procedure mainly through the VHDL to achieve a stopwatch design
Platform: | Size: 526336 | Author: 朱余建 | Hits:

[VHDL-FPGA-Verilog] 333

Description: 课程设计设计主要使用了VHDL语言，采用的开发软件是Quartus-II，设计一个循环彩灯控制器和数字显示秒表。在Quartus-II开发平台下进行了编译、仿真。-Cycle lantern controller and digital display stopwatch
Platform: | Size: 191488 | Author: 麦琪 | Hits:

[Documents] EDA-24秒倒计时程序

Description: 本秒表计时器用于体育竞赛及各种要求有较精确时的各领域。此计时器是用一块专用的芯片，用VHDL语言描述的。它除开关、时钟和显示功能以外，它还包括1/100s计时器所有的控制和定时功能，其体积小，携带方便。(The stopwatch timer is used in sports competitions and in various fields where requirements are more accurate. This timer is written in a VHDL language using a dedicated chip. In addition to switching, clocking and display functions, it also includes 1/100s timers, all control and timing functions, which are small in size and easy to carry.)
Platform: | Size: 3072 | Author: 白米粥 | Hits:

[Other] ise

Description: 在ise软件上，用VHDL语言，设计的数字跑表，可以两位计数，含分频器，计数器(In the ISE software, using VHDL language digital stopwatch design, can two counts, including frequency divider, counter)
Platform: | Size: 762880 | Author: uestczzz | Hits:
« 1 2 ... 4 5 6 7 8 9»

CodeBus www.codebus.net